Ultralow Saturation Voltage in WS2 Source-Gated Transistors with Self-Aligned and Fermi-Level-Depinned Contacts
2025 · ACS Applied Electronic Materials
저자
Seongyun Yang, Dong-Gyu Lee, 김지현 (Jihyun Kim)
연구주제
2D Materials and Applications · Advancements in Semiconductor Devices and Circuit Design
NTIS 과학기술표준분류
가장 가까운 분류(전기/전자 > 반도체 소자·회로)가 화학·화공 범위 밖이다. 배정 근거: 지원 과제·키워드 근거가 없어 AI가 논문 제목·초록을 읽고 고른 분류.
AI 연구 키워드·방법
fermi level pinning self aligned contact doping source gated transistor 이황화텅스텐(WS2)
키워드 (OpenAlex)
tungsten disulfide transition metal dichalcogenides self-aligned contacts Fermi level pinning Schottky barrier height Al2O3 interlayer current saturation low-power electronics
초록
Transition-metal dichalcogenides (TMDs) have emerged as promising materials for overcoming the scaling limitations of conventional silicon-based electronics. However, achieving efficient current saturation at low operating voltages remains challenging for field-effect transistors based on TMDs. In this study, we develop a WS 2 -based tunnel-contact source-gated transistor (TC-SGT) using a self-aligned contact process with a T-shaped source electrode. This approach allows the formation of a sub-400 nm channel without additional lithography steps, simplifying the fabrication process. A 2 nm Al 2 O 3 layer inserted at the WS 2 –metal interface significantly reduces the Fermi-level pinning, increasing the Schottky barrier height from 48.5 to 90.0 meV. This configuration enables contact-controlled operation with an ultralow saturation voltage of 0.12 V, which is the lowest value reported amon…
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